Chipworks. By Dick James, Senior Technology Analyst, Chipworks. On December 3rd – 7th , the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2. IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer- scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano- scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high- speed devices, as well as process technology and device modeling and simulation.”That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy. In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order.

As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor. Saturday/Sunday. Again this year the conference starts on the Saturday afternoon, with a set of six 9.

The Struggle to Keep Scaling BEOL, and What We Can Do Next, Rod Augur, Global. Foundries. Physical Characterization of Advanced Devices, Robert Wallace, U. Texas at Dallas. Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications, Bernard Dieny, Chief Scientist, Spintec CEAElectronic Circuits and Architectures for Neuromorphic Computing Platforms, Giacomo Indiveri, U.

Zurich/ETH Zurich. Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Dr.

Ben Kaczer, imec. Technologies for Io.

T and Wearable Applications, Including Advances in Cost- Effective and Reliable Embedded Non- Volatile Memories, Ali Keshavarzi, Vice President of R& D, Cypress Semiconductor. The first three are from 2. This year I hope to make it to the Physical Characterization session, and possibly the Io. T talk at 4. 3. 0.

On Sunday December 1. Technology Options at the 5- Nanometer Node” and “Design/Technology Enablers for Computing Applications”. Baixar Gta San Andreas Full Rip Tpb Torrent. Last year the process short course was “Emerging CMOS Technology at 5 nm and Beyond”, so I guess we will see how things have evolved at 5 nm.

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The course has been organized by An Steegen and Dan Mocuta of Imec. They introduce it bright and early, at 8. The first session is “Nano Patterning Challenges at the 5nm Node”, given by. Akihisa Sekiguchi of Tokyo Electron.

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Next up is Nadine Collaert from imec, discussing “Novel Channel Materials for High- Performance and Low- Power CMOS”, followed by Aaron Thean, of the National University of Singapore (and formerly imec),who is presenting on “Options beyond Fin. FETs at 5nm node”. Contacts are the next topic, “Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance”, by Reza Arghavani of Lam Research.

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The back- end stack gets more critical as dimensions shrink, so we have a review of “Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology”, by Theodorus Standaert from IBM. The last session covers off “Metrology Challenges for 5nm Technology”, by Applied Materials’ Ofer Adan – given that we are now counting atoms, challenging is a good way to describe it. John Chen of Nvidia set up the Design/Technology short course, which takes a fairly high- level look at the technologies involved in processing Big Data, discussing the different processors themselves, the effects of memory, managing the power and connectivity, and where advanced packaging fits in.

So we have: “The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape” – Liam Madden, Xilinx“Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design and Technology Perspective” – Gabriel Molas, Leti“Power Management with Integrated Power Devices. Dally, NVIDIA/ Stanford U“Advanced Packaging Technologies for System Integration” – Douglas Yu, TSMCI would call both courses a full day, seeing as we finish at ~5. If you have the stamina, at 6.

CEA- Leti is hosting a Devices Workshop at the Nikko Hotel, across the street from the Hilton. Monday. Monday morning we have the plenary session, with three pertinent talks on the challenges and potential of contemporary electronics: “Technology Scaling Challenges and Opportunities of Memory Devices” – Seok- Hee Lee, Hynix“Brain- Inspired Computing” Dharmendra S. Modha – IBM“Symbiotic Low- Power, Smart and Secure Technologies in the age of Hyperconnectivity” – Marie- No. They claim the world’s smallest- ever SRAM cell at 0.

It also features dual- strained channels formed on a thick strain- relaxed buffer (SRB) virtual substrate to give tensile- strained NMOS and compressively strained Si. GE PMOS for the enhancement of drive current by 1. HKMG process. Epitaxy is used in the contact trenches to minimize resistance. Schematic (center) of dual- stressed channel materials on the SRB with a super- steep retrograde well (SSRW), along with TEM images of (a) the tensile- strained silicon fin and (b) the compressively- strained Si. Ge fin on a common SRB (2. TEM image of a cross- section of an optimized Si HBT device (3. Paper 3. 3 is an invited talk on “High Frequency Ga.

N HEMTs for RF MMIC Applications”, from HRL Labs. In paper 3. 4, MIT studies a new form of instability due to F- migration and the passivation/depassivation of Si dopants in a n- In. Al. As cap layer in In.

Ga. As MOSFETs; it turns out that removing the cap layer gets rid of the instability! MIT also presents paper 3. RF circuit linearity performance of Ga. N HEMTs, in both device and circuit design techniques. Ga. N HEMTs are again discussed in 3. W- band N- polar devices; UCal Santa Barbera claims a record high efficiency of 2.

GHz. And to fill in the gap at 3. IBM gives an invited talk on “Monolithic Integration of Multiple III- V Semiconductors on Si for MOSFETs and TFETs”, using template- assisted selective epitaxy (TASE) for a number of III- V compounds.

Session 4: Memory Technology — RRAM, PRAM and Applications. We start with an invited talk “Towards Ultimate Scaling Limits of Phase- Change Memory” (4. Feng Xiong of Stanford U., reviewing advances in phase- change memory (PCM), which is now down to sub- 1. Paper 4. 2 discusses confined ALD- based PCM with a metallic liner, which is reported to have record endurance of 2e.

Si. Ox- based RRAM (Resistive Random- Access Memory) in crossbar memory arrays, and also as select devices in the arrays. Oxygen implantation into Ta. O5 and Hf. O2 is used to form RRAM devices in the ON state (4. The correlation between endurance, window margin and retention of RRAM types (oxide RAM and conductive bridge RAM) is studied in 4. RAM retention is the topic in 4.

The intrinsic variability factors of RRAM are quantified in 4. Panasonic’s 4. 0- nm embedded Re. RAM process. Session 5: Nano Device Technology — 1.

D and 2. D Devices. This session (not surprisingly) is a set of research papers, starting with a pair of carbon nanotube (CNT) transistor studies; 5. CNT- FETs with nickel contacts alloyed into the ends of the CNTs to reduce contact resistance and give scalability to the contact process. Schematic of a CNT- based CMOS inverter with entirely Ni end- bonded contacts (5. We look at vertically suspended CNT- FETs in 5.

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